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SUMMARY:100 MHz sampling 1st level SD trigger for Infill Array and Auger N
 orth based on a single progressive FPGA
DTSTART;VALUE=DATE-TIME:20070706T194500Z
DTEND;VALUE=DATE-TIME:20070706T194500Z
DTSTAMP;VALUE=DATE-TIME:20260616T155759Z
UID:indico-contribution-122@cern.ch
DESCRIPTION:Speakers: Dr. SZADKOWSKI\, Zbigniew (University of Lodz)\nThe 
 proposal of a new 4th generation of the Front-End with the advanced 1st \n
 level triggers for the Infill Array of the Pierre Auger Observatory and fo
 r the \nAuger North is described. Newest FPGA chips offer much higher capa
 city of logic \nregisters and memories\, as well as DSP blocks. The calibr
 ation channel\, \npreviously supported by an external dual-port RAM\, has 
 been fully implemented \ninto FPGA chip\, through a large internal memory.
  In turn DSP blocks allowed on \nimplementation of much more sophisticated
  spectral trigger algorithms.\nA single chip simplified board design\, new
 er architecture of FPGA reduced \nresouces utilization and power consumpti
 on. Higher sampling in the new Front-\nEnd in comparison with previous 40 
 MHz designs as well as free resources for \nnew detection algotithms can b
 e a good platform for CR radio detection \ntechnique at Auger enhancing a 
 duty cycle for the detection of UHECR’s.\n\nhttps://indico.nucleares.una
 m.mx/event/4/session/39/contribution/122
LOCATION:Merida\, Mexico Regency (Hyatt)
URL:https://indico.nucleares.unam.mx/event/4/session/39/contribution/122
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