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SUMMARY:Simulation of the lpGBT chip and firmware design for the new FEC o
 f the MuonID detector in ALICE3
DTSTART;VALUE=DATE-TIME:20261020T232000Z
DTEND;VALUE=DATE-TIME:20261020T233000Z
DTSTAMP;VALUE=DATE-TIME:20261104T121845Z
UID:indico-contribution-30@cern.ch
DESCRIPTION:Speakers: Mr. MAMANI\, Beymar (BUAP)\nThe MuonID detector at A
 LICE3 at CERN\, designed to identify muons beyond the 70-cm absorber and o
 perate in triggerless mode\, requires electronic systems capable of handli
 ng up to 6\,400 channels with high granularity (50–60 mm/pad). In this c
 ontext\, simulation of the lpGBT chip is essential for validating the new 
 Front-End Card (FEC)\, ensuring high-speed optical links of up to 10 Gb/s\
 , low latency\, and precise synchronization with continuous acquisition sy
 stems. The simulation focuses on studying the eLinks signals\, which are c
 onfigurable between 80 Mb/s and 1.28 Gb/s\, evaluating their integrity\, l
 atency\, and robustness against noise. Additionally\, the firmware design 
 principles for uplink (10.24 Gb/s) and downlink (2.56 Gb/s) transmission a
 re analyzed\, along with the stability of the eClocks that synchronize the
  input/output channels. This work enables the optimization of communicatio
 n protocols and ensures compatibility with FPGA- and ASIC-based architectu
 res—a critical step for the stable operation of the MuonID detector unde
 r high-particle-density conditions and for the efficient reconstruction of
  tracks in the ALICE3 experiment.\n\nhttps://indico.nucleares.unam.mx/even
 t/2675/session/3/contribution/30
LOCATION:Puebla
URL:https://indico.nucleares.unam.mx/event/2675/session/3/contribution/30
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